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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Rev. 03 -- 27 April 2010 Product data sheet
1. General description
The 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided per 8-bit section. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standard JESD8-B CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold Output drive capability 50 transmission lines at 85 C Current drive 24 mA at VCC = 3.0 V
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
3. Ordering information
Table 1. Ordering information Temperature range -40 C to +85 C -40 C to +85 C Package Name 74ALVCH16374DL 74LVCH16374DGG SSOP48 TSSOP48 Description plastic shrink small outline package; 48 leads; body width 7.5 mm plastic thin shrink small outline package; 48 leads; body width 6.1 mm Version SOT370-1 SOT362-1 Type number
4. Functional diagram
1 1OE 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1CP 48 2CP 25
001aal770
24 2OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
Fig 1.
Logic symbol
74ALVCH16374_3
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Product data sheet
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
1OE 1CP 2OE 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1EN C1 2EN C2 1D 1 2 3 5 6 8 9 11 12 2D 2 13 14 16 17 19 20 22 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
001aal772
Fig 2.
IEC logic symbol
VCC
data input
to internal circuit
mna705
Fig 3.
Bus hold circuit
1D0
D CP
Q
1Q0
2D0
D CP
Q
2Q0
FF1 1CP 2CP
FF9
1OE
2OE
to 7 other channels
to 7 other channels
001aal771
Fig 4.
Logic diagram
74ALVCH16374_3
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Product data sheet
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
74ALVCH16374
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1 2 3 4 5 6 7 8 9 48 1CP 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2CP
001aal769
GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24
Fig 5.
Pin configuration
74ALVCH16374_3
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
Table 2. Symbol 1OE, 2OE 1Q0 to 1Q7 2Q0 to 2Q7 GND VCC 1D0 to 1D7 2D0 to 2D7 1CP, 2CP Pin description Pin 1, 24 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 47, 46, 44, 43, 41, 40, 38, 37 36, 35, 33, 32, 30, 29, 27, 26 48, 25 Description output enable input (active LOW) 3-state flip-flop outputs 3-state flip-flop outputs ground (0 V) positive supply voltage data inputs data inputs clock input
6. Functional description
6.1 Function table
Table 3. Inputs nOE L L H H
[1]
Function table[1] nCP Dn l h l h Internal flip-flops L H L H Outputs Q0 to Q7 L H Z Z load register and disable outputs Operating mode load and read register
H = HIGH voltage level; L = LOW voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; = LOW-to-HIGH clock transition; Z = high-impedance OFF-state.
74ALVCH16374_3
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Tamb = -40 C to +125 C; SSOP48 package TSSOP48 package
[1] [2] [3]
[2] [3]
Conditions VI < 0 V control inputs data inputs VO > VCC or VO < 0 V
[1] [1] [1]
Min -0.5 -50 -0.5 -0.5 -0.5 -100 -65 -
Max +4.6 +4.6 VCC + 0.5 50 VCC + 0.5 50 100 +150 850 600
Unit V mA V V mA V mA mA mA C mW mW
VO = 0 V to VCC
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Above 55 C the value of Ptot derates linearly with 11.3 mW/K. Above 55 C the value of Ptot derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 5. Symbol VCC Recommended operating conditions Parameter supply voltage Conditions maximum speed performance CL = 30 pF CL = 50 pF low voltage applications VI VO Tamb t/V input voltage output voltage ambient temperature in free air VCC = 3.0 V to 3.6 V input transition rise and fall rate VCC = 2.3 V to 3.0 V data inputs control inputs 2.3 3.0 1.2 0 0 0 -40 0 0 2.7 3.6 3.6 VCC 5.5 VCC +85 20 10 V V V V V V C ns/V ns/V Min Typ Max Unit
74ALVCH16374_3
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol VIH Parameter HIGH-level input voltage Conditions VCC = 1.2 V VCC = 1.8 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL LOW-level input voltage VCC = 1.2 V VCC = 1.8 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 1.8 V to 3.6 V IO = -6 mA; VCC = 1.8 V IO = -6 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -18 mA; VCC = 2.3 V IO = -24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.8 V to 3.6 V IO = 6 mA; VCC = 1.8 V IO = 6 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 18 mA; VCC = 2.3 V IO = 24 mA; VCC = 3.0 V II input leakage current VCC = 1.8 V to 3.6 V control input; VI = 5.5 V or GND data input; VI = VCC or GND IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND VCC = 1.8 V to 2.7 V VCC = 2.7 V to 3.6 V ILIZ OFF-state input leakage current VI = VCC or GND VCC = 1.8 V to 2.7 V VCC = 3.6 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 1.8 V to 2.7 V VCC = 2.7 V to 3.6 V 0.1 0.2 20 40 A A 0.1 0.1 10 15 A A 0.1 0.1 5 10 A A 0.1 0.1 5 5 A A 0 0.09 0.07 0.15 0.14 0.23 0.27 0.20 0.30 0.20 0.40 0.40 0.60 0.55 V V V V V V V VCC - 0.2 VCC - 0.4 VCC - 0.3 VCC - 0.5 VCC - 0.5 VCC - 0.6 VCC - 1.0 VCC VCC - 0.1 VCC - 0.08 VCC - 0.17 VCC - 0.14 VCC - 0.26 VCC - 0.28 V V V V V V V Min VCC 0.7VCC 1.7 2.0 Typ[1] 0.9 1.2 1.5 0.9 1.2 1.5 Max 0 0.7 0.8 Unit V V V V V V V Tamb = -40 C to +85 C
0.2VCC V
74ALVCH16374_3
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Table 6. Static characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol ICC Parameter additional supply current Conditions VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V per control input per data I/O input IBHL IBHH IBHLO IBHHO CI
[1] [2]
Min
Typ[1]
Max
Unit
[2] [2] [2] [2] [2] [2] [2] [2]
5 150 150 -175 5.0
500 750 -
A A A A A A A A A A pF
bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current input capacitance
VCC = 2.3 V; VI = 0.7 V VCC = 3.0 V; VI = 0.8 V VCC = 2.3 V; VI = 1.7 V VCC = 3.0 V; VI = 2.0 V VCC = 2.7 V VCC = 3.6 V VCC = 2.7 V VCC = 3.6 V
45 75 -45 -75 300 450 -300 -450 -
All typical values are measured at Tamb = 25 C. Valid for data inputs of bus hold parts only.
10. Dynamic characteristics
Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 9. Symbol fmax Parameter maximum frequency Conditions see Figure 6 VCC = 1.8 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tpd propagation delay nCP to nQn; see Figure 6 VCC = 1.2 V VCC = 1.8 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V ten enable time nOE to nQn; see Figure 7 VCC = 1.2 V VCC = 1.8 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V
[3] [2] [3] [4] [2] [3] [4] [2]
Min
Typ[1]
Max
Unit
Tamb = -40 C to +85 C 125 150 150 200 1.5 1.0 1.0 1.0 1.5 1.0 1.0 1.0 250 300 300 350 7.7 3.6 2.3 2.3 2.4 8.7 4.0 2.6 2.9 2.3 6.5 4.3 3.8 3.4 7.2 4.8 4.8 4.0 MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns
74ALVCH16374_3
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Product data sheet
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Table 7. Dynamic characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 9. Symbol tdis Parameter disable time Conditions nOE to nQn; see Figure 7 VCC = 1.2 V VCC = 1.8 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tW pulse width nCP HIGH or LOW; see Figure 6 VCC = 1.8 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsu set-up time Dn to nCP; see Figure 8 VCC = 1.8 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V th hold time Dn to nCP; see Figure 8 VCC = 1.8 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V CPD power dissipation capacitance per flip-flop; VI = GND to VCC outputs enabled outputs disabled
[1] [2] [3] [4] All typical values are measured at Tamb = 25 C. Typical values are measured at VCC = 2.5 V. Typical values are measured at VCC = 3.3 V. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs.
[3] [5] [2] [3] [2] [3] [2] [3] [2] [4]
Min 1.5 1.0 1.0 1.0 4.0 3.0 3.0 2.5 1.5 1.2 1.5 1.2 0.6 0.8 0.6 0.8 -
Typ[1] 6.2 3.1 2.1 2.9 2.6 2.0 1.6 1.6 1.4 0.2 0.2 0.4 0.2 -0.2 -0.1 -0.2 0.0 16 10
Max 5.4 4.0 4.5 4.1 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF
74ALVCH16374_3
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Product data sheet
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
11. Waveforms
1 / fmax VI nCP input GND VOH nQn output VOL VM VM
001aal773
VM tW tPHL
VM
VM
tPLH
Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load.
Fig 6.
Propagation delay, clock input (nCP) to data output (nQn), and pulse width
VI nOE input GND VM VM
tPLZ
VCC
tPZL
nQn output LOW-to-OFF OFF-to-LOW
VOL
VM VX
tPHZ
VOH
tPZH
VY VM
nQn output HIGH-to-OFF OFF-to-HIGH
GND outputs enabled
outputs disabled
outputs enabled
001aal795
Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load.
Fig 7.
3-state enable and disable times
VI nCP input GND VI nDn input GND
VM tsu
VM tsu th VM VM VM
VM
th VM
001aal774
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 8.
Data setup and hold times for input (nDn) to input (nCP)
74ALVCH16374_3
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Product data sheet
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Table 8. VCC
Measurement points Input VI VM 0.5 2.7 V 2.7 V Output VM 0.5 1.5 V 1.5 V VX VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VY VOH - 0.15 V VOH - 0.3 V VOH - 0.3 V
Supply voltage
2.3 V to 2.7 V and VCC < 2.3 V 2.7 V 3.0 V to 3.6 V 2.7 V 2.7 V
12. Test information
VEXT VCC VI VO DUT
RT CL RL RL
G
mna616
Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.
Fig 9. Table 9. VCC
Load circuit for measuring switching times Test data Input VI VCC 2.7 V 2.7 V tr, tf 2.0 ns 2.5 ns 2.5 ns Load CL 30 pF 50 pF 50 pF RL 500 500 500 VEXT tPLH, tPHL open open open tPLZ, tPZL 2 x VCC 2 x VCC 2 x VCC tPHZ, tPZH GND GND GND
Supply voltage 2.3 V to 2.7 V and < 2.3 V 2.7 V 3.0 V to 3.6 V
74ALVCH16374_3
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Product data sheet
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
13. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
D
E
A
X
c y HE vM A
Z
48 25
Q A2 A1 (A 3) Lp
1 24
A
pin 1 index L wM detail X
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 8 o 0
o
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT370-1 (SSOP48)
74ALVCH16374_3 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
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NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT362-1 (TSSOP48)
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Product data sheet
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
14. Abbreviations
Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
15. Revision history
Table 11. Revision history Release date 20100427 Data sheet status Product data sheet Change notice Supersedes 74ALVCH16374_2 Document ID 74ALVCH16374_3 Modifications:
- The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. - Legal texts have been adapted to the new company name where appropriate. - Table 7 "Dynamic characteristics": voltage ranges corrected.
74ALVCH16374_2
19980618
Product specification
-
74ALVCH16374_1
74ALVCH16374_3
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Product data sheet
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74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be
74ALVCH16374_3
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
15 of 17
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 27 April 2010
16 of 17
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
18. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 April 2010 Document identifier: 74ALVCH16374_3

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